Various metal-oxide-silicon (MOS) integrated circuit fabrication processes have been developed and used in the production of SRAM memory arrays containing thousands of these six transistor data storage circuits (cells), with each cell including two bulk pull down transistors, two load transistors, and two access transistors. The term "pull down" derives from the fact that the output nodes of these transistors are pulled down to substantially ground potential when the transistors are biased to conduction. Generally speaking, the construction and operation of these bistable transistor circuits are well known to those skilled in the art. The two pull down transistors and the two access transistors are fabricated as MOS devices within the bulk silicon substrate, whereas the two load transistors may be fabricated as thin film transistors (TFTs) and connected between the pull down transistors, respectively, and a source of supply voltage. The source, channel and drain regions of the thin film transistors have been formed in a second level of polysilicon, and the gate electrodes of these thin film transistors are part of a first level of polysilicon which is separated at the TFT channel from the second level of polysilicon by a thin gate oxide layer.
To date, all known sixteen megabit SRAM cells have been fabricated using four or more levels of polysilicon and/or metal interconnect before the formation of the upper bit lines for the cell. In addition, these SRAM cells fabricated by known processes of the prior art have exhibited certain cell stability problems as well as certain yield problems as a result of the particular manner and sequence that the various individual process steps were carried out. For example, the TFT load devices were sometimes formed over stepped, non-planar surfaces. In addition, even slight mask misalignments during IC processing caused electrical shorting between the different levels of polysilicon in the cells. It is the solution to all of the above problems to which the present invention is directed while simultaneously reducing the levels of polysilicon interconnect to a total of three (3) prior to the bit line formation.